A 12-bit high performance low cost pipeline ADC

This paper presents the design and implementation of a 2.5V 12-hit high performance and low cost pipeline Analog-to-Digital converter (ADC) architecture using CMOS technology. A modified flash ADC was employed instead of the traditional flash ADC to implement the sub-ADC in the designed pipeline ADC scheme to reduce the device complexity and attain lower system power consumption. The designed pipeline ADC architecture is operated at 400 MHz, consumes a total power of 47.7mW. Results indicates that 40% power saving is obtained at 400MHz when the modified flash ADC is used to implement the pipeline sub-ADC instead of a full flash ADC. Such pipeline ADC is the hest candidate for many applications where power and size are the major factors.